ITERATIVE MEMORY SHARED PROCESSOR ARRAY (MSPN ARCHITECTURE DESIGN FOR CHANNEL ESTIMATION OF DOWNLINK OFDM IEEE 802.16A SYSTEM

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dc.contributor.authorGalih, Savitri
dc.contributor.authorAdiono, Trio
dc.contributor.authorKurniawan, Adit
dc.contributor.authorIskandar
dc.date.accessioned2013-12-11T04:08:13Z
dc.date.accessioned2019-10-22T01:07:31Z
dc.date.available2013-12-11T04:08:13Z
dc.date.available2019-10-22T01:07:31Z
dc.date.issued2011-10-30
dc.description.abstractWiMAX communication system has spectrum alocation that enable wireless service operator to operate throughout the world including the rural area. WiMAX is suitable for development country condition, where wiring infrastructures are limited. This advantages make WiMAX become a desirable future wireless technology that can be implemented in an developed archipelago country like Indonesia. WiMAX Communication System needs accurate channel estimation process to predict fluctuative channel condition in order to equalize received signal with the transmitted signal. Channel Estimation recent studies, mostly analyzed the algorithm side without considering implementation issue. The hardware implementation of complex signal processing algorithm such as MMSE(Minimum Mean Square Error) chamel estimation with high computational complexity. are required to achieve robust trasmission, whereas mobile wireless aplication require low power dissipation. Therefore we need an algorithm mapping method to the corresponding hardware architecture that practically fits with overall system hardware. The proposed architecture aims to achieve low power and efficient resource utilization by using iterative memory shared architecture.en_US
dc.identifier.issn1738-7906
dc.identifier.urihttp://repository.widyatama.ac.id/handle/123456789/2420
dc.language.isoenen_US
dc.publisherInternational Journal of Computer Science and Network Securityen_US
dc.subjectchannel estimation;en_US
dc.subjectOFDMen_US
dc.subjectfixed WiMAX;en_US
dc.subjectHardware Architectureen_US
dc.titleITERATIVE MEMORY SHARED PROCESSOR ARRAY (MSPN ARCHITECTURE DESIGN FOR CHANNEL ESTIMATION OF DOWNLINK OFDM IEEE 802.16A SYSTEMen_US
dc.typeArticleen_US
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