FOLDING MEMORY SHARED PROCESSOR ARRAY (FMSPA) ARCHITECTURE FOR CHANNEL ESTIMATION OF DOWNLINK OFDMA IEEE 802.16E SYSTEM
No Thumbnail Available
Date
2011-04-04
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE Computer Sociaty and University of Bedfordshire
Abstract
Abstract—The implementation of complex signal processing
algorithms are required to achieve robust transmission, whereas
mobile wireless application require low power dissipation. This
paper describes an algorithm and a corresponding hardware
architecture for the implementation of OFDMA 802.16e channel
estimation. The advantage of the proposed architecture are low
power and efficient resource utilization since we use iterative
memory shared architecture that exploits reutilization of the
processor elements and memory units. The higher data access
scheme is utilized by scheduled memory sharing with common
bus. Furthermore, we increase parallel efficiency by folding the
architecture to reduce the number of processor elements.
Description
Keywords
channel estimation, OFDMA, mobile WiMAX